Intermountain (Boise) Expo & Tech Forum

Tuesday, March 20, 2018 
Location: Boise State University
Student Union Building – Jordan D Ballroom
1910 University Drive
Boise, ID 83725

The cost to exhibit is $375/$475 (early/regular) for corporate members. The cost to exhibit for non corporate members is $450/$550 (early/regular). (click here for membership information). The cost to exhibit includes: one 6ft draped table, two chairs, company sign, lunch, directory listing and attendee list. Electricity is an additional $25 per outlet. Early bird pricing ends on Feburary 23rd, 2018!

Important Exhibitor Materials:
Please contact SMTA Expo Manager Kaitlyn Gherity with questions or for additional information.

Exhibitor Application

Advertising & Sponsorships

Discounted Hotel Rate for Exhibitors:

Hampton Inn & Suites Boise/Meridian

875 S. Allen Street

Meridian, ID 83642

Free Technical Program & Schedule:


Registration Opens

9:15am – 10:00am:

Strengths & Weaknesses of Current Stencil Technologies

Speaker: Greg Smith, Blue Ring Stencils

There are many stencil technologies available to the SMT Assembly industry. Understanding these technologies can help the SMT Engineer choose the correct technology to maximize yields and maintain costs. This presentation will explain current stencil technologies including laser and electroforming processes, stencil foil materials, step technology and nano-coating technologies currently available. Solder paste transfer efficiency data will be shown in relation to specific manufacturing processes and foil materials. Data related to the different step stencil and nano-coating technologies will also be presented. Finally, SEM analysis of different manufacturing processes and foil technologies will be shown.

Intermountain (Boise) Expo & Tech Forum
There are many stencil technologies available to the SMT Assembly industry. Understanding these technologies can help the SMT Engineer choose the correct technology to maximize yields and maintain costs


Expo Opens

11:00am – 11:45am:

How does Controlling Only Two Process Principles of Adhesives and Coatings Avoid Most Material Failure Mechanisms?

Speaker: Robert Hubbard, Ph.D., Lambda Technologies

Many apparently different reliability failure problems can be traced back to a misunderstanding of basic material properties and the effects of temperature in assembly processes. Common industry practices in the design and manufacture of electronic products are based on incorrect assumptions and or misleading information about the choice, use, and process specifications of the organic adhesives, coatings, and dielectrics used in conjunction with metals, glasses, and semiconductor components. Fundamental thermomechanical properties of organic materials, their measurements, and their limits will be examined with examples of preventable failure mechanisms. Some simple basic rules will be provided to avoid these failure mechanisms in the design and process development stages of assembly and production of microelectronic packages.

12:00pm – 1:00pm:

Complimentary Lunch 

1:00pm – 1:45pm:

Understanding Lead-Tinning Requirements for Improved Quality and Reliability 

Speaker: Roger Cox, Component Tinning Services

This paper examines the need for a two, dynamic flow, solder pot, molten solder lead tinning process, what it achieves, and how it is successfully implemented and proven from a solderability proof perspective, including results obtained from XRF analysis, wetting balance measurements and ionic cleanliness testing, in conjunction and in compliance with IPC/EIA JSTD-001, IPC/EIA JSTD-002 and ANSI/GEIA STD-0006 standards.

2:30pm – 3:15pm

Voids in Solder Joints

Speaker: Raiyo Aspandiar, Intel Corporation

Voids in solder joints continues to be a hot topic of discussion within the electronics manufacturing industry. The main interest stems from the impact that these voids have on the long term reliability of solder joints. But, not all solder joints voids are the same. This presentation will describe various types of voids observed in many types of solder joints. These void types include: Macrovoids, also called process voids, and inclusion voids specifically for leaded solder joints, which are the most widely known and studied voids in the literature; Planar Microvoids, also called champagne voids, which are mainly observed when soldering to certain types of surface finishes; Shrinkage Voids, also called sink holes, which are more common to lead-free Sn-Ag-Cu(SAC) solders than tin-lead solders, Micro Via voids, which are caused by vias in PCB lands; Pin hole voids, which are initially seen on the un-soldered PCB lands, and Intermetallic Compound (IMC) voids which generally occur within the IMC formed between two metals that have different diffusion rates within each other. Each category of Voids in Solder Joints will be described, their known root causes explained, ways of minimizing or even eliminating them will be listed, and the commonly understood effects of these voids on solder joint reliability will be discussed.


Expo Closes

For more information you can visit SMTA